The present subject matter relates to a termination resistance circuit which is used for a calibration circuit, an output driver, etc., and more particularly, to a technique for improving resolution while increasing the resistance value range of a termination resistance circuit.
A variety of semiconductor devices embodied by an integrated circuit chip, such as a CPU, a memory and a gate array, have been combined in electrical products such as a personal computer, a server and a work station. In most cases, the semiconductor devices are provided with a receiving circuit for receiving signals from the outside through input pads and an output circuit for providing internal signals to the outside through output pads.
As the operating speed of electronic products becomes faster, a swing width of signals interfaced between the semiconductor devices decreases for minimizing delay time taken for signal transmission. However, as the swing width decreases, external noise interference increases and signal reflection due to impedance mismatching at an interface stage becomes critical.
Such impedance mismatching may be caused by external noise, variation of power supply voltage, changes in operating temperature, and variations during manufacturing processes. If the impedance mismatching is created, it is difficult to transmit the data at high speed and the data outputted from an output terminal of the semiconductor device may be distorted. Therefore, in case that the semiconductor device at the receiving side receives the distorted output signal through its input terminal, the problems such as setup/hold failure or misjudgment of an input level may be caused frequently.
In particular, the semiconductor device, in which the high speed operation is required, employs an impedance matching circuit, which is called on-die termination, in the vicinity of a pad within the integrated circuit chip in order to solve the aforementioned problems. Generally, according to the on-die termination scheme, a source termination is carried out at the transmitting side by the output circuit and a parallel termination is performed at the receiving side by a termination circuit which is coupled in parallel to a receiving circuit connected to the input pad.
Meanwhile, a ZQ calibration refers to a process of generating calibration codes which are varied with Process, Voltage, and Temperature (PVT) conditions. The termination resistance is calibrated by using the calibration codes which are generated by the result of the ZQ calibration.
Hereinafter, a calibration circuit for generating calibration codes and a termination circuit for terminating input/output nodes by using the generated calibration codes will be described in detail.
FIG. 1 is a block diagram of a conventional calibration circuit.
Referring to FIG. 1, the conventional calibration circuit includes a first pull-up termination resistance circuit 110, a second pull-up termination resistance circuit 120, a pull-down termination resistance circuit 130, a reference voltage generator 102, comparators 103 and 104, and counters 105 and 106.
In operation, the comparator 103 compares a voltage of a ZQ node, which is generated by dividing a voltage between a reference resistor 101 (generally, 240Ω) and the first pull-up termination resistance circuit 110, with a reference voltage VREF (generally, set to ½VDDQ) generated from the reference voltage generator 102, to thereby generate an up/down signal UP/DOWN.
The counter 105 receives the up/down signals and then generates a pull-up calibration code PCODE<0:N>. The generated pull-up calibration code PCODE<0:N> turns on/off parallel transistors in the first pull-up termination resistance circuit 110, thereby calibrating the resistance of the first pull-up termination resistance circuit 110. The calibrated resistance of the first pull-up termination resistance circuit 110 affects the voltage at the ZQ node, and this operation is repeated. As a result, the pull-up calibration code PCODE<0:N> is counted until the total resistance value of the first pull-up termination resistance unit 110 becomes identical to the resistance value of the external resistance 101, which is called a pull-up calibration.
The pull-up calibration code PCODE<0:N> generated by the pull-up calibration process is then inputted to the second pull-up termination resistance circuit 120 to determine the total resistance value of the second pull-up termination resistance circuit 120. Similar to the pull-up calibration, a pull-down calibration starts in such a manner that a voltage of a node A becomes the same as the reference voltage VREF by using the comparator 104 and the counter 106. In other words, a pull-down calibration is performed such that the total resistance value of the pull-down termination resistance circuit 130 becomes the same as that of the second pull-up termination resistance circuit 120.
The calibration codes PCODE<0:N> and NCODE<0:N> resulting from the ZQ calibration are then inputted to a termination circuit (shown in FIG. 2), so as to calibrate the termination resistance values.
FIG. 2 is a block diagram of a conventional termination circuit.
The termination circuit refers to a circuit for terminating actual input/output pads by receiving the calibration codes PCODE<0:N> and NCODE<0:N> generated from the calibration circuit as shown in FIG. 1. Shown in FIG. 2 is an output driver of a memory device as an example of the termination circuit.
In a semiconductor memory device, the output driver is a portion for outputting data, and, as shown in FIG. 2, includes pre-drivers 210 and 220 provided at the up and down stages, a pull-up termination resistance circuit 230 and a pull-down termination resistance circuit 240 for outputting data. The pull-up termination resistance circuit 230 and the pull-down termination resistance circuit 240 of the output driver have the same configuration as the pull-up termination resistance circuit 110 and the pull-down termination resistance circuit 130 of the calibration circuit.
In brief operation, the pre-drivers 210 and 220 provided at the up and down stages control the pull-up termination resistance circuit 230 and the pull-down termination resistance circuit 240, respectively. When outputting ‘high’ data, the pull-up termination resistance circuit 230 is turned on to bring a data pin DQ to ‘high’ state, and when outputting ‘low’ data, the pull-down termination resistance circuit 240 is turned on to bring the data pin DQ to ‘low’ state. That is, the data pin DQ needs to be terminated by pull-up or pull-down to output ‘high’ or ‘low’ data.
At this moment, the pull-up calibration code PCODE<0:N> and the pull-down calibration code NCODE<0:N> determine which resistors to turn on among the parallel resistors in the pull-up termination resistance circuit 230 and the pull-down termination resistance circuit 240 that are turned on. That is, while whether to turn on the pull-up termination resistance circuit 230 and whether to turn on the pull-down termination resistance circuit 240 are determined depending on a logic state of output data, the on/off of each of the resistors in the termination resistance circuits 230 and 240 to be turned on is determined by the calibration codes PCODE<0:N> and NCODE<0:N>.
For reference, target resistance values of the pull-up termination resistance circuit 230 and the pull-down termination resistance circuit 240 are not always identical to the resistance values (240Ω) of the calibration resistance circuits (110, 120, and 130 in FIG. 1), but may have a value of 120Ω and 60Ω which is ½ and ¼ of 240Ω.
For instance, when two resistance circuits 230 and 240 of 240Ω are connected in parallel, they will have a resistance value of 120Ω, and when four are connected in parallel, they will have a resistance value of 60Ω.
DQp_CTRL and DQn_CTRL inputted to the pre-drivers 210 and 220 of FIG. 2 represent a bundle of various control signals inputted to the pre-drivers 210 and 220.
The calibration code PCODE<0:N> is also inputted to an on-die termination resistance circuit at an input buffer side. The input buffer side may perform only pull-up termination or only pull-down termination of input/output pads DQ based on the type and specification of a memory device. In this case, only the pull-up calibration code PCODE<0:N> or pull-down calibration code NCODE<0:N> is used. The on-die termination resistance circuit provided at the input buffer side also has the same configuration as the termination resistance circuits 110, 120, 130, 230, and 240 as illustrated above.
Depending on the type of a memory device, the output driver plays a role of the on-die termination resistance circuit of the input buffer. This is because the output driver plays a role of terminating the input/output pads DQ as well (however, the resistance values may be varied depending on regulations).
FIG. 3 illustrates in more detail the termination resistance circuits 110, 120, 130, 230, and 240.
The upper part of the drawing illustrates the pull-up termination resistance circuit 110, 120, and 230 whose resistance value is determined upon receipt of the pull-up calibration code PCODE<0:6>, and the lower part of the drawing illustrates the pull-down termination circuit 130 and 240 whose resistance value is determined upon receipt of the pull-down calibration code NCODE<0:6>.
The termination resistance circuits 230 and 240 used for the output driver (FIG. 2) does not directly receive the calibration codes PCODE<0:6> and NCODE<0:6>, and are controlled by the pre-drivers 210 and 220. However, when the pre-drivers 210 and 220 turn on the corresponding termination resistance circuits 230 and 240, the calibration codes PCODE<0:6> and NCODE<0:6> received by themselves are directly transmitted to the termination resistance circuits 230 and 240. Thus, in FIG. 3, the illustration is made with respect to a case where the termination resistance circuits 230 and 240 also receive the calibration codes PCODE<0:6> and NCODE<0:6>.
The parallel resistors in the termination resistance circuits 110, 120, 130, 230, and 240 have their respective binary weights. That is, the resistance values of the parallel resistors in the resistance circuits 110, 120, 130, 230, and 240 are different from each other, so that the resistance circuits 110, 120, 130, 230, and 240 can have more various resistance values. Of course, all the parallel resistors in the termination resistance circuits may be designed to have the same resistance value. In this case, however, the termination resistance circuits 110, 120, 130, 230, and 240 have less various resistance values.
FIG. 4 illustrates a case that the termination resistance circuits 110, 120, 130, 230, and 240 have resistors that are always turned on upon operation of the resistance circuits.
Referring to FIG. 4, the termination resistance circuits 110, 120, 130, 230, and 240 may be designed to have resistors that are always turned on upon operation.
Referring to FIG. 3, the resistors receiving PCODE<6> and NCODE<6> which are Most Significant Bit (MSB) codes among the calibration codes will be almost always turned on. This is because variations of the resistance values will be very large even if the resistors receiving PCODE<6> and NCODE<6> are turned off.
Accordingly, if the resistors are always turned on during operation, it is advantageous to have resistors that are controlled not by the calibration codes PCODE<6> and NCODE<6> but by other signals ON/OFF_U and ON/OFF_D. This is because a memory device requires a lot of transmission lines to transmit the calibrations codes PCODE<0:N> and NCODE<0:N> to the output driver provided in a plurality of DQ pads (where a recent memory is provided with 32 DQ pads) from the calibration circuit in the vicinity of a ZQ pad, and if the number of bits of the calibration codes PCODE<0:N> and NCODE<0:N> can be decreased, the number of transmission lines can also be decreased as much.
However, since the entire resistors in the resistance circuits 110, 120, 130, 230, and 240 may not be operated regardless of the calibration codes PCODE<0:N> and NCODE<0:N>, the termination resistance circuits 110, 120, 130, 230, and 240 are configured such that the resistors which are always turned on upon operation are turned on/off by control of the signals ON/OFF_U and ON/OFF_D.
For instance, the pull-up termination resistance circuit 230 of the output driver is operated when outputting ‘high’ data, while it is not operated when outputting ‘low’ data. Thus, the signal ON/OFF_U turns on the resistors controlled by itself only when outputting ‘high’ data, whereas the signal ON/OFF_U turns off the resistors controlled by itself when outputting ‘low’ data.
Likewise, the pull-down termination resistance circuit 240 of the output driver is operated when outputting ‘low’ data, while it is not operated when outputting ‘high’ data. Thus, the signal ON/OFF_D turns on the resistors controlled by itself only when outputting ‘low’ data, while the signal ON/OFF_D turns off the resistors controlled by itself when outputting ‘high’ data.
FIGS. 5A and 5B illustrate the range of resistance values of the termination resistance circuits 110, 120, 130, 230, and 240.
FIG. 5A shows the range of resistance values of the termination resistance circuits 110, 120, 130, 230, and 240 as the calibration codes PCODE<0:N> and NCODE<0:N> are varied under a typical condition. As shown in FIG. 5A, a target resistance value is within the range of resistance values available for the termination resistance circuits 110, 120, 130, 230, and 240.
FIG. 5B shows the range of resistance values of the termination resistance circuits 110, 120, 130, 230, and 240 as the calibration codes PCODE<0:N> and NCODE<0:N> are varied under the worst condition. Here, the worst condition refers to a case that the respective resistance values of the parallel resistors in the termination resistance circuits 110, 120, 130, 230, and 240 are changed greatly due to variations of the PVT condition. In this case, the range of resistance values of the termination resistance circuits 110, 120, 130, 230, and 240 is quite different from that of the typical condition, and, as shown in FIG. 5B, a target resistance value may not be included within the range of resistance values of the termination resistance circuits 110, 120, 130, 230, and 240. In this case, the termination resistance circuits 110, 120, 130, 230, and 240 do not have appropriate resistance values, so that data transmission/reception is not properly performed.
This problem can be solved by increasing the range of resistance values of the termination resistance circuits 110, 120, 130, 230, and 240. However, the range of resistance values of the termination resistance circuits 110, 120, 130, 230, and 240 is in a trade-off relationship with the resolution of the resistance circuits 110, 120, 130, 230, and 240.
If the total resistance value of the resistance circuits 110, 120, 130, 230, and 240 is designed to be slightly changed each time the respective calibration codes PCODE<0:N> and NCODE<0:N> are increased or decreased one by one, the resolution of the termination circuits 110, 120, 130, 230, and 240 increases but the range of resistance values available for the resistance circuits 110, 120, 130, 230, and 240 decreases. However, if the resistance values of the resistance circuits 110, 120, 130, 230, and 240 are designed to be changed greatly each time the respective calibration codes PCODE<0:N> and NCODE<0:N> are increased or decreased one by one, the range of resistance values of the resistance circuits 110, 120, 130, 230, and 240 increases but the resistance values of the resistance circuits 110, 120, 130, 230, and 240 cannot be finely calibrated.
As a method for increasing the range of resistance values of the resistance circuits 110, 120, 130, 230, and 240 while maintaining a constant resolution, there can be considered a method of increasing the number of bits of the calibration codes PCODE<0:N> and NCODE<0:N> and increasing the number of parallel resistors in the resistance circuits 110, 120, 130, 230, and 240. However, this method increases the area of the calibration circuit (in FIG. 1), increases the number of transmission lines for transmission of the calibration codes PCODE<0:N> and NCODE<0:N>, and increases the area of the output driver (in FIG. 2, a memory device has 32 output drivers), which thereby causes a serious drawback in terms of the area of a semiconductor device.